Staff Engineer - GPU Physical Design

Position Summary

Samsung is a world leader in Memory, LCD and System LSI technologies. We are currently looking for exceptional software and hardware talent to join our Samsung Austin R & D Center (SARC) in Austin, TX and our Advanced Computing Lab (ACL) in San Jose, CA. SARC was established in Austin, TX in 2010 to be one of Samsung’s strategic investments in high performance low power ARM based device technology. Presently our GPU design teams, located in Austin (SARC) and San Jose (ACL), are developing a GPU that will be deployed in Samsung mobile products. Our System IP team located in Austin (SARC) is working on Coherent Interconnect and memory controller architectures.Physical design engineer, you will work as part of GPU IP working on significant deliverables for the team. This is a mid to senior level position where the candidate will be in an individual contributor role, tasked with driving synthesis, block and full chip implementation through sign-off with the latest industry P&R/STA flows and tools. Significant block level floor-planning, implementing and optimizing the design to meet aggressive performance/power and area targets will be critical for success.

Role and Responsibilities

Key responsibilities include:

•Hands-on responsibility from synthesis to place and route of a GPU block through signoff flows including timing and physical verification

•Synthesis, Floor plan, Place & Route in chip-level and hierarchical physical implementation environment

•Running MBIST and DFT insertion into block, understanding impact of MBIST/Scan and debug logic is desirable

•Interact with RTL counterpart to resolve design issues pertaining to block closure

•Optimize GPU block to meet aggressive power/performance/area targets

Minimum requirements:

•BSEE, Computer Engineer or comparable and  7 + years of experience

•Solid understanding and working knowledge of the SOC/ASIC/GPU/CPU design flow with some experience in taping out designs

•Hands-on experience with synthesis, block and full chip implementation with the latest industry P&R/STA flows and tools

•Experience in block level floor-planning, implementing power grid and power/area/performance optimization

•Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python

•Solid understanding of Electrical Engineering fundamentals, analytical aptitude and excellent attention to detail

•Strong communication skills, team player working in collaborative work environment, discipline and planning; ability to execute with high quality deliverables is a must

Skills and Qualifications

Preferred candidate will possess the following:

•Experience with 16nm Finfet or smaller process nodes

•Experience with design implementation of GPU blocks and standard industry standard tools is advantageous

•Ability to read Verilog is preferred

•Hands-on experience with clock tree synthesis (CTS)

•Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure is an added advantage

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United States
  • R
  • Perl